Motorola programming software cps v14.0
SH-4 based standard chips were introduced around 1998. SH-4 featured superscalar (2-way) instruction execution and a vector floating-point unit (particularly suited to 3d graphics). In 1997, Hitachi and STMicroelectronics (STM) started collaborating on the design of the SH-4 for the Dreamcast. A derivative of the DSP was also used with the original SH-2 core.īetween 19, 35.1 million SuperH devices were shipped worldwide. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core unified the DSP and the RISC processor world. The SH-3 core also added a DSP extension, then called SH-3-DSP. The SH-3 was bi-endian, running in either big-endian or little-endian byte ordering. These features required an extended instruction set, adding six new instructions for a total of 68. SH-3 Ī few years later, the SH-3 core was added to the family new features included another interrupt concept, a memory management unit (MMU), and a modified cache concept. The SH-1 and the SH-2 were used in the Sega Saturn, Sega 32X and Capcom CPS-3. The SH-2 added 64-bit multiplication and a few additional commands for branching and other duties, bringing the total to 62 supported instructions. The SH-1 was the basic model, supporting a total of 56 instructions. Some instructions used these last four bits for offsets in array accesses, while others combined the second register slot and last four bits to produce an 8-bit constant. The instruction itself was also four bits, leaving another four bits unaccounted.
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In the SuperH ISA, there were only 16 registers, requiring four bits for the source and another four for the destination. The downsides to this approach were that there were fewer bits available to encode a register number or a constant value.
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The ISA uses 16-bit instructions for better code density than 32-bit instructions, which was a great benefit at the time, due to the high cost of main memory. For instance, the initial models in the line, the SH-1 and SH-2, differed only in their support for 64-bit multiplication the SH-2 supported MUL, DMULS and DMULU, whereas the SH-1 would cause a trap if these were encountered. To address this, Hitachi instead developed a single ISA for the entire line, with unsupported instructions causing traps on those implementations that didn't include hardware support. One of the key realizations during the development of the RISC concept was that the microcode had a finite decoding time, and as processors became faster, this represented an unacceptable performance overhead.
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For instance, an instruction to perform a 32 x 32 -> 64-bit multiply, a "long multiply", might be implemented in hardware on high-end models but instead be performed as a series of additions on low-end models. In the past, this sort of design problem would have been solved using microcode, with the low-end models in the series performing non-implemented instructions as a series of more basic instructions.
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The design concept was for a single instruction set (ISA) that would be upward compatible across a series of CPU cores. The SuperH processor core family was first developed by Hitachi in the early 1990s. This concept is now known as a compressed instruction set and is also used by other companies, the most notable example being ARM for its Thumb instruction set.Īs of 2015, many of the original patents for the SuperH architecture are expiring and the SH-2 CPU has been reimplemented as open source hardware under the name J2. This allowed the machine code to continue using the shorter instructions to save memory, while not demanding the amount of instruction decoding logic needed if they were completely separate instructions. Later versions of the design, starting with SH-5, included both 16- and 32-bit instructions, with the 16-bit versions mapping onto the 32-bit version inside the CPU. But for the market the SuperH was aimed at, this was a small price to pay for the improved memory and processor cache efficiency.
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Using smaller instructions had consequences, the register file was smaller and instructions were generally two-operand format. This was a novel approach at the time, RISC processors always used an instruction size that was the same as the internal data width, typically 32-bits. It is implemented by microcontrollers and microprocessors for embedded systems.Īt the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. SH2: 16-bit instructions SH2A and newer: mixed 16- and 32-bit instructions Instruction set architecture by Hitachi SuperH (SH) Designer